Electronic systems typically store data during operation in a memory device. In recent years, the dynamic random access memory (DRAM) has become a popular data storage device for such systems. Basically, a DRAM is an integrated circuit that stores data in binary form (e.g., "1" or "0") in a large number of cells. The data is stored in a cell as a charge on a capacitor located within the cell. Typically, the cells of a DRAM are arranged in an array so that individual cells can be addressed and accessed. The array can be thought of as rows and columns of cells. Each row includes a word line that interconnects all of the cells on the row with a common control signal. Similarly, each column includes a digit line that is coupled to at most one cell in each row. Thus, the word and digit lines can be controlled so as to individually access each cell of the array.
To read data out of a cell, the capacitor of a cell is accessed by selecting the word line associated with the cell. A complimentary digit line that is paired with the digit line for the selected cell is equilibrated with the voltage on the digit line for the selected cell. When the word line is activated for the selected cell, the capacitor of the selected cell discharges the stored voltage onto the digit line, thus changing the voltage on the digit line. A sense amplifier detects and amplifies the difference in voltage on the pair of digit lines. An input/output device for the array, typically an n-channel transistor, passes the voltage on the digit line for the selected cell to an input/output line for communication to, for example, a processor of a computer or other electronic system associated with the DRAM. In a write operation, data is passed from the input/output lines to the digit lines by the input/output device of the array for storage on the capacitor in the selected cell.
One problem with DRAM design relates to sizing of the input/output devices of the memory array. Typically, the input/output devices are n-channel transistors that are two to eight times smaller than the transistors in the sense amplifier. The ratio of transistor sizes used in a specific design results from trade-offs that relate to the two distinct operations of the input/output device, namely reading and writing data. During a read operation, the input/output device should not affect the voltage on the digit lines. If the input/output devices are too big (e.g., provide too small of a resistance between the sense amplifier and the input/output lines), the input/output devices can trigger the parasitic capacitance of the input/output lines or imbalances in the layout of the sense amplifier such that the data on the digit lines is corrupted. Conversely, during a write operation, the input/output devices need to be able to trigger the sense amplifier to move the voltage on the digit lines to the power supply voltage and ground potential. If the input/output devices of the array are too small, the devices will not provide sufficient current for triggering the sense amplifier when data is to be written to a selected cell over the digit line. Thus, conventional designs require a trade-off with respect to sizing the input/output devices of the memory array.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved circuit and method for reading and writing data in an array of a memory device.